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Rampage Extreme - Testing Report

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Rampage Extreme - Testing Report

Postby Greg » Thu Sep 25, 2008 5:17 am

Test System

Cooling
    CPU: Swiftech MCP655 -> Thermochill PA 120.3 (3-2000RPM Ultra Kaze) -> Swiftech MCP655 -> Thermochill PA 120.3 (3-2000RPM Ultra Kaze) -> Swiftech GTZ Cpu Block -> EK Multi-res ->
    Case: 8x Yate Loon Low RPM (Side Panel) , 1 High RPM 120mm (RAM), 2 120mm (HD Cages)
Motherboard:Rampage Extreme , Bios Version 0501 [Driver] Intel Chipset Utility 9.0.0.1008 ,Marvell Yukon Gigabit V10.60.6.3
NIC: Intel Pro PT PCI-E nic [Driver] Version 13.1.2
Power Supply: Mushkin XP-800AP
Processor: Intel Q9650
RAM: Mushkin XP3-12800 7-7-7-20 1.85v-1.95v 996657 In White Ram Slots
Sound Card: Auzentech X-FI Prelude 7.1 [Driver] Version RC6
Storage: 6x Seagate 7200.10 250GB raid 0 (ICH9R) , 1x Seagate 7200.10 250GB (eSata) [Driver] Intel Matrix Storage Manager 8.5.0.1032
Video Card: Palit HD4870X2 [Driver] Catalyst Software Suite 8.9

Tools Used
HCI Memtest Pro
cpuZ 1.47
Prime95 25.6 X64
Greg
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Re: Rampage Extreme Testing

Postby Greg » Thu Sep 25, 2008 5:19 am

400x9 1600Mhz 7-7-7-20-1N
Prime95 25.6 X64 ~4 Hours and HCI Memtest ~300%
ImageImage

Timings
ImageImageImageImage


Extreme Tweaker
Ai Overclock Tuner: Manual
OC From Memory Level Up: Auto
FSB Frequency: 400
CPU Ratio Setting: 09.0
CPU Configuration
    CPU Ratio Setting: 09.0
    C1E Support: Disabled
    CPU TM Function: Disabled
    Max CPUID Value Limit: Disabled
    Vanderpool Technology: Enabled
    Execute Disable Bit: Enabled
    Core Multi-Processing: Enabled
CPU Clock Skew: Auto
NB Clock Skew: Auto
FSB Strap to North Bridge: Auto
PCIE Frequency: 100
DRAM Frequency: 1601Mhz
DRAM Command Rate: 1N
DRAM Timing Control: Manual
1st Information: 7-7-7-20-6-82-6-3
CAS# Latency: 7
RAS# to CAS# Delay: 7
RAS# Pre Time: 7
RAS# ACT Time: 20
RAS# To RAS# Delay: 6
REF Cycle Time: 82
WRITE Recovery Time: 6
READ to Pre Time: 3
2nd Information : 9-4-5-4-6-4-6
READ to WRITE Delay (S/D): 9
WRITE to READ Delay (S): 4
WRITE to READ Delay (D): 5
READ to READ (S): 4
READ to READ (D): 6
WRITE to WRITE (S): 4
WRITE to WRITE (D): 6
3RD Information: 18-7-1-9-9
WRITE to PRE Delay: 18
READ to PRE Delay: 7
PRE to PRE Delay: 1
ALL PRE to ACT Delay: 9
ALL PRE to REF Delay: 9
DRAM Static Read Control: Enabled
DRAM Dynamic Write Control: Enabled
DRAM Skew Control
    DRAM CMD Skew on Channel A: Auto
    DRAM CLK Skew on DIMM A1: Auto
    DRAM CLK Skew on DIMM A2: Auto
    DRAM CTL Skew on DIMM A1: Auto
    DRAM CTL Skew on DIMM A2: Auto
    DRAM CMD Skew on Channel B: Auto
    DRAM CLK Skew on DIMM B1: Auto
    DRAM CLK Skew on DIMM B2: Auto
    DRAM CTL Skew on DIMM B1: Auto
    DRAM CTL Skew on DIMM B2: Auto
Ai Clock Twister: Lighter
Ai Transaction Booster: Manual
    Common Performance Level: 06
    Pull-In of CHA PH1: Disabled
    Pull-In of CHA PH2: Disabled
    Pull-In of CHA PH3: Disabled
    Pull-In of CHB PH1: Disabled
    Pull-In of CHB PH2: Disabled
    Pull-In of CHB PH3: Disabled
EPU II Phase Control: Auto
CPU Voltage: 1.15000
Load-Line Calibration: Enabled
CPU PLL Voltage: 1.51106
FSB Termination Voltage: 1.10016
CPU GTLVerf (0): Auto
CPU GTLVerf (1): Auto
CPU GTLVerf (2): Auto
CPU GTLVerf (3): Auto
NB GTLVerf: Auto
North Bridge Voltage: 1.25922
DRAM Voltage: 1.78931
NB DDRVref: Auto
DDR3 ChannelA Vref: Auto
DDR3 ChannelB Vref: Auto
South Bridge 1.5 Voltage: 1.51106
South Bridge 1.05 Voltage: 1.06039
CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled

Advanced menu
North Bridge Chipset Configuration
Memory Remap Feature: Enabled
Initiate Graphic Adapter:
PEG Port Control:
Greg
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Re: Rampage Extreme Testing

Postby Greg » Thu Sep 25, 2008 5:19 am

480x9 1600Mhz 7-7-7-20-1N
~1500% HCI Memtest
Image
Timings
ImageImageImageImage

Extreme Tweaker
Ai Overclock Tuner: Manual
OC From Memory Level Up: Auto
FSB Frequency: 480
CPU Ratio Setting: 09.0
CPU Configuration
    CPU Ratio Setting: 09.0
    C1E Support: Disabled
    CPU TM Function: Disabled
    Max CPUID Value Limit: Disabled
    Vanderpool Technology: Enabled
    Execute Disable Bit: Enabled
    Core Multi-Processing: Enabled
CPU Clock Skew: Auto
NB Clock Skew: Auto
FSB Strap to North Bridge: Auto
PCIE Frequency: 100
DRAM Frequency: 1601Mhz
DRAM Command Rate: 1N
DRAM Timing Control: Manual
1st Information: 7-7-7-20-6-82-6-3
CAS# Latency: 7
RAS# to CAS# Delay: 7
RAS# Pre Time: 7
RAS# ACT Time: 20
RAS# To RAS# Delay: 6
REF Cycle Time: 82
WRITE Recovery Time: 6
READ to Pre Time: 3
2nd Information : 9-4-5-4-6-4-6
READ to WRITE Delay (S/D): 9
WRITE to READ Delay (S): 4
WRITE to READ Delay (D): 5
READ to READ (S): 4
READ to READ (D): 6
WRITE to WRITE (S): 4
WRITE to WRITE (D): 6
3RD Information: 18-7-1-9-9
WRITE to PRE Delay: 18
READ to PRE Delay: 7
PRE to PRE Delay: 1
ALL PRE to ACT Delay: 9
ALL PRE to REF Delay: 9
DRAM Static Read Control: Enabled
DRAM Dynamic Write Control: Enabled
DRAM Skew Control
    DRAM CMD Skew on Channel A: Auto
    DRAM CLK Skew on DIMM A1: Auto
    DRAM CLK Skew on DIMM A2: Auto
    DRAM CTL Skew on DIMM A1: Auto
    DRAM CTL Skew on DIMM A2: Auto
    DRAM CMD Skew on Channel B: Auto
    DRAM CLK Skew on DIMM B1: Auto
    DRAM CLK Skew on DIMM B2: Auto
    DRAM CTL Skew on DIMM B1: Auto
    DRAM CTL Skew on DIMM B2: Auto
Ai Clock Twister: Lighter
Ai Transaction Booster: Manual
    Common Performance Level: 07
    Pull-In of CHA PH1: Disabled
    Pull-In of CHA PH2: Disabled
    Pull-In of CHA PH3: Disabled
    Pull-In of CHB PH1: Disabled
    Pull-In of CHB PH2: Disabled
    Pull-In of CHB PH3: Disabled
EPU II Phase Control: Auto
CPU Voltage: 1.38750
Load-Line Calibration: Enabled
CPU PLL Voltage: 1.55081
FSB Termination Voltage: 1.37841
CPU GTLVerf (0): +70mV
CPU GTLVerf (1): +70mV
CPU GTLVerf (2): +70mV
CPU GTLVerf (3): +70mV
NB GTLVerf: +60mV
North Bridge Voltage: 1.57722
DRAM Voltage: 1.78931
NB DDRVref: Auto
DDR3 ChannelA Vref: Auto
DDR3 ChannelB Vref: Auto
South Bridge 1.5 Voltage: 1.51106
South Bridge 1.05 Voltage: 1.06039
CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled

Advanced menu
North Bridge Chipset Configuration
Memory Remap Feature: Enabled
Initiate Graphic Adapter:
PEG Port Control:
Greg
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Re: Rampage Extreme - Testing Report

Postby zlojack » Thu Sep 25, 2008 9:41 am

Nice stuff, Greg!

Sweet clock on that quad, too.
zlojack
 
Posts: 20
Joined: Wed Nov 21, 2007 2:37 pm
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Re: Rampage Extreme - Testing Report

Postby Greg » Thu Sep 25, 2008 11:40 am

450x9 1800Mhz 8-8-8-24-1N
Prime95 25.6 X64 ~4.5hour and HCI Memtest ~500%
ImageImage


Timings
ImageImageImageImage

Extreme Tweaker
Ai Overclock Tuner: Manual
OC From Memory Level Up: Auto
FSB Frequency: 450
CPU Ratio Setting: 09.0
CPU Configuration
    CPU Ratio Setting: 09.0
    C1E Support: Disabled
    CPU TM Function: Disabled
    Max CPUID Value Limit: Disabled
    Vanderpool Technology: Enabled
    Execute Disable Bit: Enabled
    Core Multi-Processing: Enabled
CPU Clock Skew: Auto
NB Clock Skew: Auto
FSB Strap to North Bridge: Auto
PCIE Frequency: 100
DRAM Frequency: 1801Mhz
DRAM Command Rate: 1N
DRAM Timing Control: Manual
1st Information: 8-8-8-24-8-82-6-3
CAS# Latency: 8
RAS# to CAS# Delay: 8
RAS# Pre Time: 8
RAS# ACT Time: 24
RAS# To RAS# Delay: 8
REF Cycle Time: 82
WRITE Recovery Time: 6
READ to Pre Time: 3
2nd Information : 9-4-5-4-6-4-6
READ to WRITE Delay (S/D): 9
WRITE to READ Delay (S): 4
WRITE to READ Delay (D): 5
READ to READ (S): 4
READ to READ (D): 6
WRITE to WRITE (S): 4
WRITE to WRITE (D): 6
3RD Information: 21-7-1-9-9
WRITE to PRE Delay: 21
READ to PRE Delay: 7
PRE to PRE Delay: 1
ALL PRE to ACT Delay: 9
ALL PRE to REF Delay: 9
DRAM Static Read Control: Enabled
DRAM Dynamic Write Control: Enabled
DRAM Skew Control
    DRAM CMD Skew on Channel A: Auto
    DRAM CLK Skew on DIMM A1: Auto
    DRAM CLK Skew on DIMM A2: Auto
    DRAM CTL Skew on DIMM A1: Auto
    DRAM CTL Skew on DIMM A2: Auto
    DRAM CMD Skew on Channel B: Auto
    DRAM CLK Skew on DIMM B1: Auto
    DRAM CLK Skew on DIMM B2: Auto
    DRAM CTL Skew on DIMM B1: Auto
    DRAM CTL Skew on DIMM B2: Auto
Ai Clock Twister: Lighter
Ai Transaction Booster: Manual
    Common Performance Level: 07
    Pull-In of CHA PH1: Disabled
    Pull-In of CHA PH2: Disabled
    Pull-In of CHA PH3: Disabled
    Pull-In of CHB PH1: Disabled
    Pull-In of CHB PH2: Disabled
    Pull-In of CHB PH3: Disabled
EPU II Phase Control: Auto
CPU Voltage: 1.28675
Load-Line Calibration: Enabled
CPU PLL Voltage: 1.51106
FSB Termination Voltage: 1.10016
CPU GTLVerf (0): +70mV
CPU GTLVerf (1): +70mV
CPU GTLVerf (2): +70mV
CPU GTLVerf (3): +70mV
NB GTLVerf: +60mV
North Bridge Voltage: 1.51097
DRAM Voltage: 1.86881
NB DDRVref: Auto
DDR3 ChannelA Vref: +25mV
DDR3 ChannelB Vref: +25mV
South Bridge 1.5 Voltage: 1.51106
South Bridge 1.05 Voltage: 1.06039
CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled

Advanced menu
North Bridge Chipset Configuration
Memory Remap Feature: Enabled
Initiate Graphic Adapter:
PEG Port Control:
Retired
Greg
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